| Titre : | Offset Reduction Techniques in High-Speed Analog-to-Digital Converters : analysis, design and tradeoffs | | Type de document : | texte imprimé | | Auteurs : | Pedro M. Figueiredo, Auteur ; Joao C. Vital, Auteur | | Editeur : | New York : Springer-Verlag | | Année de publication : | 2009 | | Collection : | Analog Circuits and Signal Processing | | Importance : | 382 p. | | Présentation : | couv. ill. en coul., ill. | | Format : | 24 cm. | | ISBN/ISSN/EAN : | 978-1-402-09715-7 | | Langues : | Anglais (eng) | | Index. décimale : | 25-05 Application du traitement numérique du signal | | Résumé : | Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Since the offset voltages of the constituting sub-blocks of these converters (pre-amplifiers, folding circuits and latched comparators) present the definitive linearity limitation, the offset is the fundamental design parameter in high-speed CMOS ADCs. Consequently, offset reduction techniques must be employed, in order to achieve high frequency operation with low power and layout area. Averaging and offset sampling are the most widely used, both being thoroughly characterized:
the most exhaustive study ever performed about averaging in both pre-amplifier and folding stages is presented, covering the DC and transient responses, all mismatch sources, termination, and a fully automated design procedure;
existing offset sampling methods are carefully reviewed, and two new techniques are disclosed that, combined, yield a (nearly) offset free comparator.
Other relevant topics include kickback noise elimination in comparators, reference buffer design, a technique to compensate (certain) IR drops, details on the layout and floorplan of cascaded folding stages, and an improved scheme to select reference voltages in fine ADCs of two-step subranging converters. Special emphasis is given to the methods of guaranteeing specifications across process, temperature and supply voltage corners. | | Note de contenu : | Contents
1 High-Speed ADC Architectures. 1.1 Introduction. 1.2 The Analog-to-Digital Converter. 1.3 Flash ADCs. 1.4 Two-Step Flash ADCs. 1.5 Folding and Interpolation ADCs. 1.6 Building Blocks of CMOS High-Speed ADCs.
2 Averaging Technique - DC Analysis and Termination. 2.1 Introduction. 2.2 Published Studies on the Averaging Technique. 2.3 Output Voltage and Gain. 2.4 Effect of Mismatches - INL and DNL. 2.5 Averaging in Folding Circuits. 2.6 Considerations About the Yield. 2.7 Termination of the Averaging Network.
3 Averaging Technique - Transient Analysis and Automated Design. 3.1 Introduction. 3.2 Flash ADC Architecture. 3.3 Output Voltage and Gain. 3.4 Effect of Mismatches. 3.5 Design of Averaged Pre-Amplifier Stages in Flash ADCs.
4 Integrated Prototypes using Averaging. 4.1 Introduction. 4.2 7-bit 120 MS/s I/Q flash ADC. 4.3 10-bit 100 MS/s Folding and Interpolation ADC.
5 Offset Cancellation Methods. 5.1 Introduction. 5.2 Offset Cancellation Techniques. 5.3 New Offset Cancellation Technique. 5.4 6-bit 1 GHz Two-Step Subranging ADC.
6 Conclusions. 6.1 Overview of the Research Work.
-Appendix A Averaging with Piecewise Linear Differential Pairs. A.1 Introduction. A.2 Output Voltage and Gain. A.3 Effect of Mismatches - INL and DNL.
-Appendix B Mismatches in the Resistors of the Aveaging Network. B.1 Introduction. B.2 Mismatches in Resistors R0. B.3 Mismatches in Resistors R1.
-Appendix C Averaging in Folding Stages. C.1 Introduction. C.2 Equivalence Between Circular and Infinite Networks. C.3 Output Voltage and Gain. C.4 Effect of Mismatches. |
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters : analysis, design and tradeoffs [texte imprimé] / Pedro M. Figueiredo, Auteur ; Joao C. Vital, Auteur . - New York : Springer-Verlag, 2009 . - 382 p. : couv. ill. en coul., ill. ; 24 cm.. - ( Analog Circuits and Signal Processing) . ISBN : 978-1-402-09715-7 Langues : Anglais ( eng) | Index. décimale : | 25-05 Application du traitement numérique du signal | | Résumé : | Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Since the offset voltages of the constituting sub-blocks of these converters (pre-amplifiers, folding circuits and latched comparators) present the definitive linearity limitation, the offset is the fundamental design parameter in high-speed CMOS ADCs. Consequently, offset reduction techniques must be employed, in order to achieve high frequency operation with low power and layout area. Averaging and offset sampling are the most widely used, both being thoroughly characterized:
the most exhaustive study ever performed about averaging in both pre-amplifier and folding stages is presented, covering the DC and transient responses, all mismatch sources, termination, and a fully automated design procedure;
existing offset sampling methods are carefully reviewed, and two new techniques are disclosed that, combined, yield a (nearly) offset free comparator.
Other relevant topics include kickback noise elimination in comparators, reference buffer design, a technique to compensate (certain) IR drops, details on the layout and floorplan of cascaded folding stages, and an improved scheme to select reference voltages in fine ADCs of two-step subranging converters. Special emphasis is given to the methods of guaranteeing specifications across process, temperature and supply voltage corners. | | Note de contenu : | Contents
1 High-Speed ADC Architectures. 1.1 Introduction. 1.2 The Analog-to-Digital Converter. 1.3 Flash ADCs. 1.4 Two-Step Flash ADCs. 1.5 Folding and Interpolation ADCs. 1.6 Building Blocks of CMOS High-Speed ADCs.
2 Averaging Technique - DC Analysis and Termination. 2.1 Introduction. 2.2 Published Studies on the Averaging Technique. 2.3 Output Voltage and Gain. 2.4 Effect of Mismatches - INL and DNL. 2.5 Averaging in Folding Circuits. 2.6 Considerations About the Yield. 2.7 Termination of the Averaging Network.
3 Averaging Technique - Transient Analysis and Automated Design. 3.1 Introduction. 3.2 Flash ADC Architecture. 3.3 Output Voltage and Gain. 3.4 Effect of Mismatches. 3.5 Design of Averaged Pre-Amplifier Stages in Flash ADCs.
4 Integrated Prototypes using Averaging. 4.1 Introduction. 4.2 7-bit 120 MS/s I/Q flash ADC. 4.3 10-bit 100 MS/s Folding and Interpolation ADC.
5 Offset Cancellation Methods. 5.1 Introduction. 5.2 Offset Cancellation Techniques. 5.3 New Offset Cancellation Technique. 5.4 6-bit 1 GHz Two-Step Subranging ADC.
6 Conclusions. 6.1 Overview of the Research Work.
-Appendix A Averaging with Piecewise Linear Differential Pairs. A.1 Introduction. A.2 Output Voltage and Gain. A.3 Effect of Mismatches - INL and DNL.
-Appendix B Mismatches in the Resistors of the Aveaging Network. B.1 Introduction. B.2 Mismatches in Resistors R0. B.3 Mismatches in Resistors R1.
-Appendix C Averaging in Folding Stages. C.1 Introduction. C.2 Equivalence Between Circular and Infinite Networks. C.3 Output Voltage and Gain. C.4 Effect of Mismatches. |
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