Titre :	Logic synthesis using synopsys®
Type de document :	texte imprimé
Auteurs :	Pran Kurup, Auteur ; Taher Abbasi, Auteur
Mention d'édition :	2 ed.
Editeur :	Boston, Dordrecht, London : Kluwer Academic Publishers
Année de publication :	1996
Importance :	322 p.
Présentation :	couv. ill. en en coul
Format :	23,7 cm.
ISBN/ISSN/EAN :	978-0-7923-9786-1
Langues :	Anglais (eng)
Mots-clés :	VHDL, Verilog, computer-aided design (CAD), design, logic, model, simulation, stability
Index. décimale :	24-03 Programmation des microsystèmes et microprocesseurs
Résumé :	Logic Synthesis Using Synopsys®, Second Edition is for anyone who hates reading manuals but would still like to learn logic synthesis as practised in the real world. Synopsys Design Compiler, the leading synthesis tool in the EDA marketplace, is the primary focus of the book. The contents of this book are specially organized to assist designers accustomed to schematic capture-based design to develop the required expertise to effectively use the Synopsys Design Compiler. Over 100 `Classic Scenarios' faced by designers when using the Design Compiler have been captured, discussed and solutions provided. These scenarios are based on both personal experiences and actual user queries. A general understanding of the problem-solving techniques provided should help the reader debug similar and more complicated problems. In addition, several examples and dc_shell scripts (Design Compiler scripts) have also been provided. Logic Synthesis Using Synopsys®, Second Edition is an updated and revised version of the very successful first edition. The second edition covers several new and emerging areas, in addition to improvements in the presentation and contents in all chapters from the first edition. With the rapid shrinking of process geometries it is becoming increasingly important that `physical' phenomenon like clusters and wire loads be considered during the synthesis phase. The increasing demand for FPGAs has warranted a greater focus on FPGA synthesis tools and methodology. Finally, behavioral synthesis, the move to designing at a higher level of abstraction than RTL, is fast becoming a reality. These factors have resulted in the inclusion of separate chapters in the second edition to cover Links to Layout, FPGA Synthesis and Behavioral Synthesis, respectively. Logic Synthesis Using Synopsys®, Second Edition has been written with the CAD engineer in mind. A clear understanding of the synthesis tool concepts, its capabilities and the related CAD issues will help the CAD engineer formulate an effective synthesis-based ASIC design methodology. The intent is also to assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools.
Note de contenu :	Table of contents CHAPTER 1 High-Level Design Methodology Overview 1.1 ASIC Design Flow Using Synthesis 1.2 Design Compiler Basics 1.3 Classic Scenarios CHAPTER 2 VHDL/Verilog Coding for Synthesis 2.1 General HDL Coding Issues 2.2 VHDL vs. Verilog: The Language Issue 2.3 Finite State Machines 2.4 HDL Coding Examples 2.5 Classic Scenarios CHAPTER 3 Pre and Post-Synthesis Simulation 3.1 RTL Simulation 3.2 File Text IO in VHDL Using the TEXTIO Package 3.3 VHDL Gate Level Simulation 3.4 Verilog Gate Level Simulation 3.5 Classic Scenarios CHAPTER 4 Constraining and Optimizing Designs 4.1 Synthesis Background 4.2 Clock Specification for Synthesis 4.3 Design Compiler Timing Reports 4.4 Commonly Used Design Compiler Commands 4.5 Strategies for Compiling Designs 4.6 Typical Scenarios When Optimizing Designs 4.7 Guidelines for Logic Synthesis 4.8 Classic Scenarios CHAPTER 5 Constraining and Optimizing Designs 5.1 Finite State Machine (FSM) Synthesis 5.2 Fixing Min Delay Violations 5.3 Technology Translation 5.4 Translating Designs with Black-Box Cells 5.5 Pad Synthesis 5.6 Classic Scenarios CHAPTER 6 Links to Layout 6.1 Motivation for Links to Layout 6.2 Floorplanning 6.3 Link to Layout Flow Using FloorPlan Manager 6.4 Basic Links to Layout Commands 6.5 Creating Wire Load Models After Back-Annotation 6.6 Re-Optimizing Designs After P&R 6.7 Classic Scenarios CHAPTER 7 Synthesis 7.1 FPGAs vs. ASICs 7.2 Xilinx 4000 Architecture 7.3 Synopsys Setup (.synopsys_dc.setup) For Xilinx 7.4 Synopsys FPGA Compiler Flow CHAPTER 8 Design for Testability 8.1 Introduction to Test Synthesis 8.2 Test Synthesis Using Test Compiler 8.3 Design-Specific Issues in Test Synthesis 8.4 Clock Skew 8.5 Test Compiler Default Test Protocol 8.6 Test Compiler Tips 8.7 Examples Showing the Entire Test Synthesis Flow 8.8 Classic Scenarios CHAPTER 9 Between CAD Tools 9.1 Electronic Data Interchange Format (EDIF) 9.2 Forward and Back-annotation 9.3 Design Compiler Input/Output Formats 9.4 Classic Scenarios CHAPTER 10 Design Re-Use Using DesignWare 10.1 DesignWare Libraries 10.2 Inferring Complex Cells 10.3 Creating Your Own Design Ware Library 10.4 Classic Scenarios CHAPTER 11 Synthesis - An Introduction 11.1 Logic Synthesis 11.2 Behavioral Synthesis Concepts 11.3 Synopsys Behavioral Compiler 11.4 Behavioral Synthesis Design Flow 11.5 Example Using Behavioral Compiler 11.6 Behavioral Compiler Reports 11.7 Is Behavioral Synthesis Right For You? 11.8 Classic Scenarios Appendix A Sample dc_shell Scripts Sample Synopsys Technology Library Sample Synopsys Technology RAM Library Model.

Logic synthesis using synopsys® [texte imprimé] / Pran Kurup, Auteur ; Taher Abbasi, Auteur  . -  2 ed. . - Boston, Dordrecht, London : Kluwer Academic Publishers, 1996 . - 322 p. : couv. ill. en en coul ; 23,7 cm.
ISBN : 978-0-7923-9786-1
Langues : Anglais (eng)

Mots-clés :	VHDL, Verilog, computer-aided design (CAD), design, logic, model, simulation, stability
Index. décimale :	24-03 Programmation des microsystèmes et microprocesseurs
Résumé :	Logic Synthesis Using Synopsys®, Second Edition is for anyone who hates reading manuals but would still like to learn logic synthesis as practised in the real world. Synopsys Design Compiler, the leading synthesis tool in the EDA marketplace, is the primary focus of the book. The contents of this book are specially organized to assist designers accustomed to schematic capture-based design to develop the required expertise to effectively use the Synopsys Design Compiler. Over 100 `Classic Scenarios' faced by designers when using the Design Compiler have been captured, discussed and solutions provided. These scenarios are based on both personal experiences and actual user queries. A general understanding of the problem-solving techniques provided should help the reader debug similar and more complicated problems. In addition, several examples and dc_shell scripts (Design Compiler scripts) have also been provided. Logic Synthesis Using Synopsys®, Second Edition is an updated and revised version of the very successful first edition. The second edition covers several new and emerging areas, in addition to improvements in the presentation and contents in all chapters from the first edition. With the rapid shrinking of process geometries it is becoming increasingly important that `physical' phenomenon like clusters and wire loads be considered during the synthesis phase. The increasing demand for FPGAs has warranted a greater focus on FPGA synthesis tools and methodology. Finally, behavioral synthesis, the move to designing at a higher level of abstraction than RTL, is fast becoming a reality. These factors have resulted in the inclusion of separate chapters in the second edition to cover Links to Layout, FPGA Synthesis and Behavioral Synthesis, respectively. Logic Synthesis Using Synopsys®, Second Edition has been written with the CAD engineer in mind. A clear understanding of the synthesis tool concepts, its capabilities and the related CAD issues will help the CAD engineer formulate an effective synthesis-based ASIC design methodology. The intent is also to assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools.
Note de contenu :	Table of contents CHAPTER 1 High-Level Design Methodology Overview 1.1 ASIC Design Flow Using Synthesis 1.2 Design Compiler Basics 1.3 Classic Scenarios CHAPTER 2 VHDL/Verilog Coding for Synthesis 2.1 General HDL Coding Issues 2.2 VHDL vs. Verilog: The Language Issue 2.3 Finite State Machines 2.4 HDL Coding Examples 2.5 Classic Scenarios CHAPTER 3 Pre and Post-Synthesis Simulation 3.1 RTL Simulation 3.2 File Text IO in VHDL Using the TEXTIO Package 3.3 VHDL Gate Level Simulation 3.4 Verilog Gate Level Simulation 3.5 Classic Scenarios CHAPTER 4 Constraining and Optimizing Designs 4.1 Synthesis Background 4.2 Clock Specification for Synthesis 4.3 Design Compiler Timing Reports 4.4 Commonly Used Design Compiler Commands 4.5 Strategies for Compiling Designs 4.6 Typical Scenarios When Optimizing Designs 4.7 Guidelines for Logic Synthesis 4.8 Classic Scenarios CHAPTER 5 Constraining and Optimizing Designs 5.1 Finite State Machine (FSM) Synthesis 5.2 Fixing Min Delay Violations 5.3 Technology Translation 5.4 Translating Designs with Black-Box Cells 5.5 Pad Synthesis 5.6 Classic Scenarios CHAPTER 6 Links to Layout 6.1 Motivation for Links to Layout 6.2 Floorplanning 6.3 Link to Layout Flow Using FloorPlan Manager 6.4 Basic Links to Layout Commands 6.5 Creating Wire Load Models After Back-Annotation 6.6 Re-Optimizing Designs After P&R 6.7 Classic Scenarios CHAPTER 7 Synthesis 7.1 FPGAs vs. ASICs 7.2 Xilinx 4000 Architecture 7.3 Synopsys Setup (.synopsys_dc.setup) For Xilinx 7.4 Synopsys FPGA Compiler Flow CHAPTER 8 Design for Testability 8.1 Introduction to Test Synthesis 8.2 Test Synthesis Using Test Compiler 8.3 Design-Specific Issues in Test Synthesis 8.4 Clock Skew 8.5 Test Compiler Default Test Protocol 8.6 Test Compiler Tips 8.7 Examples Showing the Entire Test Synthesis Flow 8.8 Classic Scenarios CHAPTER 9 Between CAD Tools 9.1 Electronic Data Interchange Format (EDIF) 9.2 Forward and Back-annotation 9.3 Design Compiler Input/Output Formats 9.4 Classic Scenarios CHAPTER 10 Design Re-Use Using DesignWare 10.1 DesignWare Libraries 10.2 Inferring Complex Cells 10.3 Creating Your Own Design Ware Library 10.4 Classic Scenarios CHAPTER 11 Synthesis - An Introduction 11.1 Logic Synthesis 11.2 Behavioral Synthesis Concepts 11.3 Synopsys Behavioral Compiler 11.4 Behavioral Synthesis Design Flow 11.5 Example Using Behavioral Compiler 11.6 Behavioral Compiler Reports 11.7 Is Behavioral Synthesis Right For You? 11.8 Classic Scenarios Appendix A Sample dc_shell Scripts Sample Synopsys Technology Library Sample Synopsys Technology RAM Library Model.