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Affiner la recherche Interroger des sources externesAcquisition de données en technologie CMOS 0.25µm / Fayçal Meddour
Titre : Acquisition de données en technologie CMOS 0.25µm : conception simulation et réalisation Type de document : texte imprimé Auteurs : Fayçal Meddour, Auteur ; Zohir Dibi, Auteur Editeur : Allemagne : Édition Universitaires Européennes Année de publication : 2014 Importance : 128 p. Présentation : couv. ill. en en coul Format : 21,6 cm. ISBN/ISSN/EAN : 978-3-84173-194-4 Langues : Français (fre) Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : Du fait des développements technologiques, des systèmes électroniques réalisés sous forme de cartes, sont intégrés et sur une seule puce. Cet ouvrage tente de rassembler et présenter les différente technologiques (, CMOS, DMOS) dan la conception. Nous avons réalisé en collaboration avec le groupe de recherche de l’institut de la Microélectronique de l’université de Berlin, un travail de recherche pour le développement d’une bibliothèque analogique adaptée spécialement au circuit intégré. Enfin, nous exposons dans une dernière partie les différentes issues de conception et réalisation du Layout en introduisant la majorité des problèmes rencontrés ainsi que leurs solutions. Nous exposons le Layout réalisé pour la chaine d’acquisition. Une conclusion ponctue ce document, suivie des annexes techniques. Note de contenu : Sommaire
I.1.Introduction
I.2.Conception analogique
I.3.Conception d'un VLSI
I.4.Circuit intégrés ASICs
I.5.Aperçu sur la technologie des semi-conducteurs
II.2.Transistor MOS
II.4.Les miroires de courant en technologie CMOS
II.5.L'amplificateur opérationnel idéal
II.6.La structure rail à rail
III.2.Cahier de charge
III.3 Distributeur de courant
III.4.Simulation du distributeur de courant
III.5.Multiplexeur à 16 entrées
III.6.Driver de tension contrôle
IV.2.Layout
IV.3.Le cycle d'un circuit layout
IV.4.Les couches de masques
IV.5.Les techniques de layout
IV.6.Layout des différents blocs de notre projetAcquisition de données en technologie CMOS 0.25µm : conception simulation et réalisation [texte imprimé] / Fayçal Meddour, Auteur ; Zohir Dibi, Auteur . - Allemagne : Édition Universitaires Européennes, 2014 . - 128 p. : couv. ill. en en coul ; 21,6 cm.
ISBN : 978-3-84173-194-4
Langues : Français (fre)
Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : Du fait des développements technologiques, des systèmes électroniques réalisés sous forme de cartes, sont intégrés et sur une seule puce. Cet ouvrage tente de rassembler et présenter les différente technologiques (, CMOS, DMOS) dan la conception. Nous avons réalisé en collaboration avec le groupe de recherche de l’institut de la Microélectronique de l’université de Berlin, un travail de recherche pour le développement d’une bibliothèque analogique adaptée spécialement au circuit intégré. Enfin, nous exposons dans une dernière partie les différentes issues de conception et réalisation du Layout en introduisant la majorité des problèmes rencontrés ainsi que leurs solutions. Nous exposons le Layout réalisé pour la chaine d’acquisition. Une conclusion ponctue ce document, suivie des annexes techniques. Note de contenu : Sommaire
I.1.Introduction
I.2.Conception analogique
I.3.Conception d'un VLSI
I.4.Circuit intégrés ASICs
I.5.Aperçu sur la technologie des semi-conducteurs
II.2.Transistor MOS
II.4.Les miroires de courant en technologie CMOS
II.5.L'amplificateur opérationnel idéal
II.6.La structure rail à rail
III.2.Cahier de charge
III.3 Distributeur de courant
III.4.Simulation du distributeur de courant
III.5.Multiplexeur à 16 entrées
III.6.Driver de tension contrôle
IV.2.Layout
IV.3.Le cycle d'un circuit layout
IV.4.Les couches de masques
IV.5.Les techniques de layout
IV.6.Layout des différents blocs de notre projetExemplaires
Code-barres Cote Support Localisation Section Disponibilité N.Inventaire 3945 27-05-12 Livre Bibliothèque de Génie Electrique- USTO Documentaires Exclu du prêt 3945
Titre : Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® Type de document : texte imprimé Auteurs : Himanshu Bhatnagar, Auteur Mention d'édition : 2nd. ed. Editeur : Boston, Dordrecht, London : Kluwer Academic Publishers Année de publication : 2002 Importance : 328 p. Présentation : couv. ill. en coul., ill. Format : 24,1 cm. ISBN/ISSN/EAN : 978-0-7923-7644-6 Langues : Anglais (eng) Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : Advanced ASIC Chip Synthesis: Using Synopsys® DesignCompiler® Physical Compiler® and PrimeTime®, SecondEdition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.Note de contenu : Sommaire
Chapter 1. ASIC Design Methodology.
2. Tutorial.
3. Basic Concepts.
4. Synopsis Technology Library.
5. Partitioning and Coding Styles.
6. Constraining Designs.
7. Optimizing Designs.
8. Design for Test.
9. Links to Layout & Post Layout OPT.
10. Physical Synthesis.
11. SDF Generation.
12. Primetime Basics.
13. Static Timing Analysis.
Appendix A.
Appendix B.
Index.Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® [texte imprimé] / Himanshu Bhatnagar, Auteur . - 2nd. ed. . - Boston, Dordrecht, London : Kluwer Academic Publishers, 2002 . - 328 p. : couv. ill. en coul., ill. ; 24,1 cm.
ISBN : 978-0-7923-7644-6
Langues : Anglais (eng)
Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : Advanced ASIC Chip Synthesis: Using Synopsys® DesignCompiler® Physical Compiler® and PrimeTime®, SecondEdition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.Note de contenu : Sommaire
Chapter 1. ASIC Design Methodology.
2. Tutorial.
3. Basic Concepts.
4. Synopsis Technology Library.
5. Partitioning and Coding Styles.
6. Constraining Designs.
7. Optimizing Designs.
8. Design for Test.
9. Links to Layout & Post Layout OPT.
10. Physical Synthesis.
11. SDF Generation.
12. Primetime Basics.
13. Static Timing Analysis.
Appendix A.
Appendix B.
Index.Exemplaires
Code-barres Cote Support Localisation Section Disponibilité N.Inventaire 1537 27-05-06 Livre Bibliothèque de Génie Electrique- USTO Documentaires Exclu du prêt 1537
Titre : Advanced Semiconductor Heterostructures : novel devices, potential device applications and basic properties Type de document : texte imprimé Auteurs : Mitra Dutta, Auteur ; Michael A. Stroscio, Auteur Editeur : Singapore, New jersey, London, Hong kong : World Scientific Publishing Co. Année de publication : 2003 Collection : Selected Topics in Electronics and Systems Importance : 233 p. Présentation : ill. Format : 25,4 cm. ISBN/ISSN/EAN : 978-981-238-289-4 Langues : Anglais (eng) Catégories : SEMI CONDUCTEURS Index. décimale : 27-01 Technologie des matériaux à semi-conducteur Résumé : This volume provides valuable summaries on many aspects of advanced semiconductor heterostructures and highlights the great variety of semiconductor heterostructures that has emerged since their original conception. As exemplified by the chapters in this book, recent progress on advanced semiconductor heterostructures spans a truly remarkable range of scientific fields with an associated diversity of applications. Some of these applications will undoubtedly revolutionize critically important facets of modern technology. At the heart of these advances is the ability to design and control the properties of semiconductor devices on the nanoscale. As an example, the intersubband lasers discussed in this book have a broad range of previously unobtainable characteristics and associated applications as a result of the nanoscale dimensional control of the underlying semiconductor heterostructures. As this book illustrates, an astounding variety of heterostructures can be fabricated with current technology; the potentially widespread use of layered quantum dots fabricated with nanoscale precision in biological applications opens up exciting advances in medicine. In addition, many more excellent examples of the remarkable impact being made through the use of semiconductor heterostructures are given. The summaries in this volume provide timely insights into what we know now about selected areas of advanced semiconductor heterostructures and also provide foundations for further developments. Note de contenu : CONTENTS
-NOVEL HETERSTRUCTURE DEVICES
ELECTRON-PHONON INTERACTIONS IN INTERSUBBAND LASER HETEROSTRUCTURES
QUANTUM DOT INFRARED DETECTORS AND SOURCES
Generation of Terahertz Emission Based on Intersubband Transitions
MID-INFRARED GaSb-BASED LASERS WITH TYPE-I HETEROINTERFACES
ADVANCES IN QUANTUM-DOT RESEARCH AND TECHNOLOGY: THE PATH TO APPLICATION IN BIOLOGY
-POTENTIAL DEVICE APPLICATIONS AN BASIC PROPERTIES
HIGH-FIELD ELECTRON TRANSPORT CONTROLLED BY OPTICAL PHONON EMISSION IN NITRIDES
COOLING BY INVERSE NOTTINGHAM EFFECT WITH RESONANT TUNNELING
THE PHYSICS OF SINGLE ELECTRON TRANSISTORS
CARRIER CAPTURE AND TRANSPORT WITHIN TUNNEL INJECTION LASERS: A QUANTUM TRANSPORT ANALYSIS
THE INFLUENCE OF ENVIRONMENTAL EFFECTS ON THE ACOUSTIC PHONON SPECTRA IN QUANTUM-DOT HETEROSTRUCTURES
QUANTUM DEVICES WITH MULTIPOLE-ELECTRODE - HETEROJUNCTIONS HYBRID STRUCTURESAdvanced Semiconductor Heterostructures : novel devices, potential device applications and basic properties [texte imprimé] / Mitra Dutta, Auteur ; Michael A. Stroscio, Auteur . - Singapore, New jersey, London, Hong kong : World Scientific Publishing Co., 2003 . - 233 p. : ill. ; 25,4 cm.. - (Selected Topics in Electronics and Systems) .
ISBN : 978-981-238-289-4
Langues : Anglais (eng)
Catégories : SEMI CONDUCTEURS Index. décimale : 27-01 Technologie des matériaux à semi-conducteur Résumé : This volume provides valuable summaries on many aspects of advanced semiconductor heterostructures and highlights the great variety of semiconductor heterostructures that has emerged since their original conception. As exemplified by the chapters in this book, recent progress on advanced semiconductor heterostructures spans a truly remarkable range of scientific fields with an associated diversity of applications. Some of these applications will undoubtedly revolutionize critically important facets of modern technology. At the heart of these advances is the ability to design and control the properties of semiconductor devices on the nanoscale. As an example, the intersubband lasers discussed in this book have a broad range of previously unobtainable characteristics and associated applications as a result of the nanoscale dimensional control of the underlying semiconductor heterostructures. As this book illustrates, an astounding variety of heterostructures can be fabricated with current technology; the potentially widespread use of layered quantum dots fabricated with nanoscale precision in biological applications opens up exciting advances in medicine. In addition, many more excellent examples of the remarkable impact being made through the use of semiconductor heterostructures are given. The summaries in this volume provide timely insights into what we know now about selected areas of advanced semiconductor heterostructures and also provide foundations for further developments. Note de contenu : CONTENTS
-NOVEL HETERSTRUCTURE DEVICES
ELECTRON-PHONON INTERACTIONS IN INTERSUBBAND LASER HETEROSTRUCTURES
QUANTUM DOT INFRARED DETECTORS AND SOURCES
Generation of Terahertz Emission Based on Intersubband Transitions
MID-INFRARED GaSb-BASED LASERS WITH TYPE-I HETEROINTERFACES
ADVANCES IN QUANTUM-DOT RESEARCH AND TECHNOLOGY: THE PATH TO APPLICATION IN BIOLOGY
-POTENTIAL DEVICE APPLICATIONS AN BASIC PROPERTIES
HIGH-FIELD ELECTRON TRANSPORT CONTROLLED BY OPTICAL PHONON EMISSION IN NITRIDES
COOLING BY INVERSE NOTTINGHAM EFFECT WITH RESONANT TUNNELING
THE PHYSICS OF SINGLE ELECTRON TRANSISTORS
CARRIER CAPTURE AND TRANSPORT WITHIN TUNNEL INJECTION LASERS: A QUANTUM TRANSPORT ANALYSIS
THE INFLUENCE OF ENVIRONMENTAL EFFECTS ON THE ACOUSTIC PHONON SPECTRA IN QUANTUM-DOT HETEROSTRUCTURES
QUANTUM DEVICES WITH MULTIPOLE-ELECTRODE - HETEROJUNCTIONS HYBRID STRUCTURESExemplaires
Code-barres Cote Support Localisation Section Disponibilité N.Inventaire 2885 27-01-12 Livre Bibliothèque de Génie Electrique- USTO Documentaires Exclu du prêt 2885
Titre : Analog integrated circuit design Type de document : texte imprimé Auteurs : Tony Chan Carusone, Auteur ; David A. Johns, Auteur ; Kenneth W. Martin, Auteur Mention d'édition : 2 ed. Editeur : Singapore : John wiley & sons, inc / International student version Année de publication : 2013 Importance : 792 p. Présentation : couv. ill. en en coul Format : 23,2 cm. ISBN/ISSN/EAN : 978-1-11-809233-0 Langues : Anglais (eng) Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : When first published this text by David Johns and Kenneth Martin quickly became a leading textbook for the advanced course on Analog IC Design. This new edition has been thoroughly revised and updated but continues the central themes of the first edition which made it so sucessful.
This edition features extensive new material on CMOS IC device modeling, processing and layout. Coverage has been added on several types of circuits that have increased in importance in the past decade, such as generalized integer-N phase locked loops and their phase noise analysis, voltage regulators, and 1.5b-per-stage pipelined A/D converters. Two new chapters have been added to make the book more accessible to beginners in the field: frequency response of analog ICs; and basic theory of feedback amplifiers.Note de contenu : CONTENTS
CHAPTER 1 INTEGRATED-CIRCUIT DEVICES AND MODELLING
1.1 Semiconductors and pn Junctions
1.2 MOS Transistors
1.3 Device Model Summary
1.4 Advanced MOS Modelling
1.5 SPICE Modelling Parameters
1.6 Passive Devices
CHAPTER 2 PROCESSING AND LAYOUT
2.1 CMOS Processing
2.2 CMOS Layout and Design Rules
2.3 Variability and Mismatch
2.4 Analog Layout Considerations
CHAPTER 3 BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS
3.1 Simple CMOS Current Mirror
3.2 Common-Source Amplifier
3.3 Source-Follower or Common-Drain Amplifier
3.4 Common-Gate Amplifier
3.5 Source-Degenerated Current Mirrors
3.6 Cascode Current Mirrors
3.7 Cascode Gain Stage
3.8 MOS Differential Pair and Gain Stage
CHAPTER 4 FREQUENCY RESPONSE OF ELECTRONIC CIRCUITS
4.1 Frequency Response of Linear Systems
4.2 Frequency Response of Elementary Transistor Circuits
4.3 Cascode Gain Stage
4.4 Source-Follower Amplifier
4.5 Differential Pair
CHAPTER 5 FEEDBACK AMPLIFIERS
5.1 Ideal Model of Negative Feedback
5.2 Dynamic Response of Feedback Amplifiers
5.3 First- and Second-Order Feedback Systems
5.4 Common Feedback Amplifiers
CHAPTER 6 BASIC OPAMP DESIGN AND COMPENSATION
6.1 Two-Stage CMOS Opamp
6.2 Opamp Compensation
6.3 Advanced Current Mirrors
6.4 Folded-Cascode Opamp
6.5 Current Mirror Opamp
6.6 Linear Settling Time Revisited
6.7 Fully Differential Opamps
6.8 Common-Mode Feedback Circuits
CHAPTER 7 BIASING, REFERENCES, AND REGULATORS
7.1 Analog Integrated Circuit Biasing
7.2 Establishing Constant Transconductance
7.3 Establishing Constant Voltages and Currents
7.4 Voltage Regulation
CHAPTER 8 BIPOLAR DEVICES AND CIRCUITS
8.1 Bipolar-Junction Transistors
8.2 Bipolar Device Model Summary
8.3 SPICE Modeling
8.4 Bipolar and BICMOS Processing
8.5 Bipolar Current Mirrors and Gain Stages
CHAPTER 9 NOISE AND LINEARITY ANALYSIS AND MODELLING
9.1 Time-Domain Analysis
9.2 Frequency-Domain Analysis
9.3 Noise Models for Circuit Elements
9.4 Noise Analysis Examples
9.5 Dynamic Range Performance
CHAPTER 10 COMPARATORS
10.1 Comparator Specifications
10.2 Using an Opamp for a Comparator
10.3 Charge-Injection Errors
10.4 Latched Comparators
10.5 Examples of CMOS and BiCMOS Comparators
10.6 Examples of Bipolar Comparators
CHAPTER 11 SAMPLE-AND-HOLD AND TRANSLINEAR CIRCUITS
11.1 Performance of Sample-and-Hold Circuits
11.2 MOS Sample-and-Hold Basics
11.3 Examples of CMOS S/H Circuits
11.4 Bipolar and BiCMOS Sample-and-Holds
11.5 Translinear Gain Cell
11.6 Translinear Multiplier
CHAPTER 12 CONTINUOUS-TIME FILTERS
12.1 Introduction to Continuous-Time Filters
12.2 Introduction to Gm-C Filters
12.3 Transconductors Using Fixed Resistors
12.4 CMOS Transconductors Using Triode Transistors
12.5 CMOS Transconductors Using Active Transistors
12.6 Bipolar Transconductors
12.7 BiCMOS Transconductors
12.8 Active RC and MOSFET-C Filters
12.9 Tuning Circuitry
12.10 Introduction to Complex Filters
CHAPTER 13 DISCRETE-TIME SIGNALS
13.1 Overview of Some Signal Spectra
13.2 Laplace Transforms of Discrete-Time Signals
13.4 Downsampling and Upsampling
13.5 Discrete-Time Filters
13.6 Sample-and-Hold Response
CHAPTER 14 SWITCHED-CAPACITOR CIRCUITS
14.1 Basic Building Blocks
14.2 Basic Operation and Analysis
14.3 Noise in Switched-Capacitor Circuits
14.4 First-Order Filters
14.5 Biquad Filters
14.6 Charge Injection
14.7 Switched-Capacitor Gain Circuits
14.8 Correlated Double-Sampling Techniques
14.9 Other Switched-Capacitor Circuits
CHAPTER 15 DATA CONVERTER FUNDAMENTALS
15.1 Ideal D/A Converter
15.2 Ideal A/D Converter
15.3 Quantization Noise
15.4 Signed Codes
15.5 Performance Limitations
CHAPTER 16 NYQUIST-RATE D/A CONVERTERS
16.1 Decoder-Based Converters
16.2 Binary-Scaled Converters
16.3 Thermometer-Code Converters
16.4 Hybrid Converters
CHAPTER 17 NYQUIST-RATE A/D CONVERTERS 646
17.1 Integrating Converters
17.2 Successive-Approximation Converters
17.3 Algorithmic (or Cyclic) A/D Converter
17.4 Pipelined A/D Converters
17.5 Flash Converters
17.6 Two-Step A/D Converters
17.7 Interpolating A/D Converters
17.8 Folding A/D Converters
17.9 Time-Interleaved A/D Converters
CHAPTER 18 OVERSAMPLING CONVERTERS
18.1 Oversampling without Noise Shaping
18.2 Oversampling with Noise Shaping
18.3 System Architectures
18.4 Digital Decimation Filters
18.5 Higher-Order Modulators
18.6 Bandpass Oversampling Converters
18.7 Practical Considerations
18.8 Multi-Bit Oversampling Converters
18.9 Third-Order A/D Design Example
CHAPTER 19 PHASE-LOCKED LOOPS
19.1 Basic Phase-Locked Loop Architecture
19.2 Linearized Small-Signal Analysis
19.3 Jitter and Phase Noise
19.4 Electronic Oscillators
19.5 Jitter and Phase Noise in PLLS
Key Points References Problems
INDEXAnalog integrated circuit design [texte imprimé] / Tony Chan Carusone, Auteur ; David A. Johns, Auteur ; Kenneth W. Martin, Auteur . - 2 ed. . - Singapore : John wiley & sons, inc / International student version, 2013 . - 792 p. : couv. ill. en en coul ; 23,2 cm.
ISBN : 978-1-11-809233-0
Langues : Anglais (eng)
Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : When first published this text by David Johns and Kenneth Martin quickly became a leading textbook for the advanced course on Analog IC Design. This new edition has been thoroughly revised and updated but continues the central themes of the first edition which made it so sucessful.
This edition features extensive new material on CMOS IC device modeling, processing and layout. Coverage has been added on several types of circuits that have increased in importance in the past decade, such as generalized integer-N phase locked loops and their phase noise analysis, voltage regulators, and 1.5b-per-stage pipelined A/D converters. Two new chapters have been added to make the book more accessible to beginners in the field: frequency response of analog ICs; and basic theory of feedback amplifiers.Note de contenu : CONTENTS
CHAPTER 1 INTEGRATED-CIRCUIT DEVICES AND MODELLING
1.1 Semiconductors and pn Junctions
1.2 MOS Transistors
1.3 Device Model Summary
1.4 Advanced MOS Modelling
1.5 SPICE Modelling Parameters
1.6 Passive Devices
CHAPTER 2 PROCESSING AND LAYOUT
2.1 CMOS Processing
2.2 CMOS Layout and Design Rules
2.3 Variability and Mismatch
2.4 Analog Layout Considerations
CHAPTER 3 BASIC CURRENT MIRRORS AND SINGLE-STAGE AMPLIFIERS
3.1 Simple CMOS Current Mirror
3.2 Common-Source Amplifier
3.3 Source-Follower or Common-Drain Amplifier
3.4 Common-Gate Amplifier
3.5 Source-Degenerated Current Mirrors
3.6 Cascode Current Mirrors
3.7 Cascode Gain Stage
3.8 MOS Differential Pair and Gain Stage
CHAPTER 4 FREQUENCY RESPONSE OF ELECTRONIC CIRCUITS
4.1 Frequency Response of Linear Systems
4.2 Frequency Response of Elementary Transistor Circuits
4.3 Cascode Gain Stage
4.4 Source-Follower Amplifier
4.5 Differential Pair
CHAPTER 5 FEEDBACK AMPLIFIERS
5.1 Ideal Model of Negative Feedback
5.2 Dynamic Response of Feedback Amplifiers
5.3 First- and Second-Order Feedback Systems
5.4 Common Feedback Amplifiers
CHAPTER 6 BASIC OPAMP DESIGN AND COMPENSATION
6.1 Two-Stage CMOS Opamp
6.2 Opamp Compensation
6.3 Advanced Current Mirrors
6.4 Folded-Cascode Opamp
6.5 Current Mirror Opamp
6.6 Linear Settling Time Revisited
6.7 Fully Differential Opamps
6.8 Common-Mode Feedback Circuits
CHAPTER 7 BIASING, REFERENCES, AND REGULATORS
7.1 Analog Integrated Circuit Biasing
7.2 Establishing Constant Transconductance
7.3 Establishing Constant Voltages and Currents
7.4 Voltage Regulation
CHAPTER 8 BIPOLAR DEVICES AND CIRCUITS
8.1 Bipolar-Junction Transistors
8.2 Bipolar Device Model Summary
8.3 SPICE Modeling
8.4 Bipolar and BICMOS Processing
8.5 Bipolar Current Mirrors and Gain Stages
CHAPTER 9 NOISE AND LINEARITY ANALYSIS AND MODELLING
9.1 Time-Domain Analysis
9.2 Frequency-Domain Analysis
9.3 Noise Models for Circuit Elements
9.4 Noise Analysis Examples
9.5 Dynamic Range Performance
CHAPTER 10 COMPARATORS
10.1 Comparator Specifications
10.2 Using an Opamp for a Comparator
10.3 Charge-Injection Errors
10.4 Latched Comparators
10.5 Examples of CMOS and BiCMOS Comparators
10.6 Examples of Bipolar Comparators
CHAPTER 11 SAMPLE-AND-HOLD AND TRANSLINEAR CIRCUITS
11.1 Performance of Sample-and-Hold Circuits
11.2 MOS Sample-and-Hold Basics
11.3 Examples of CMOS S/H Circuits
11.4 Bipolar and BiCMOS Sample-and-Holds
11.5 Translinear Gain Cell
11.6 Translinear Multiplier
CHAPTER 12 CONTINUOUS-TIME FILTERS
12.1 Introduction to Continuous-Time Filters
12.2 Introduction to Gm-C Filters
12.3 Transconductors Using Fixed Resistors
12.4 CMOS Transconductors Using Triode Transistors
12.5 CMOS Transconductors Using Active Transistors
12.6 Bipolar Transconductors
12.7 BiCMOS Transconductors
12.8 Active RC and MOSFET-C Filters
12.9 Tuning Circuitry
12.10 Introduction to Complex Filters
CHAPTER 13 DISCRETE-TIME SIGNALS
13.1 Overview of Some Signal Spectra
13.2 Laplace Transforms of Discrete-Time Signals
13.4 Downsampling and Upsampling
13.5 Discrete-Time Filters
13.6 Sample-and-Hold Response
CHAPTER 14 SWITCHED-CAPACITOR CIRCUITS
14.1 Basic Building Blocks
14.2 Basic Operation and Analysis
14.3 Noise in Switched-Capacitor Circuits
14.4 First-Order Filters
14.5 Biquad Filters
14.6 Charge Injection
14.7 Switched-Capacitor Gain Circuits
14.8 Correlated Double-Sampling Techniques
14.9 Other Switched-Capacitor Circuits
CHAPTER 15 DATA CONVERTER FUNDAMENTALS
15.1 Ideal D/A Converter
15.2 Ideal A/D Converter
15.3 Quantization Noise
15.4 Signed Codes
15.5 Performance Limitations
CHAPTER 16 NYQUIST-RATE D/A CONVERTERS
16.1 Decoder-Based Converters
16.2 Binary-Scaled Converters
16.3 Thermometer-Code Converters
16.4 Hybrid Converters
CHAPTER 17 NYQUIST-RATE A/D CONVERTERS 646
17.1 Integrating Converters
17.2 Successive-Approximation Converters
17.3 Algorithmic (or Cyclic) A/D Converter
17.4 Pipelined A/D Converters
17.5 Flash Converters
17.6 Two-Step A/D Converters
17.7 Interpolating A/D Converters
17.8 Folding A/D Converters
17.9 Time-Interleaved A/D Converters
CHAPTER 18 OVERSAMPLING CONVERTERS
18.1 Oversampling without Noise Shaping
18.2 Oversampling with Noise Shaping
18.3 System Architectures
18.4 Digital Decimation Filters
18.5 Higher-Order Modulators
18.6 Bandpass Oversampling Converters
18.7 Practical Considerations
18.8 Multi-Bit Oversampling Converters
18.9 Third-Order A/D Design Example
CHAPTER 19 PHASE-LOCKED LOOPS
19.1 Basic Phase-Locked Loop Architecture
19.2 Linearized Small-Signal Analysis
19.3 Jitter and Phase Noise
19.4 Electronic Oscillators
19.5 Jitter and Phase Noise in PLLS
Key Points References Problems
INDEXExemplaires
Code-barres Cote Support Localisation Section Disponibilité N.Inventaire 2525 27-05-08 Livre Bibliothèque de Génie Electrique- USTO Documentaires Exclu du prêt 2525 2526 27-05-08 Livre Bibliothèque de Génie Electrique- USTO Documentaires Exclu du prêt 2526
Titre : Application-specific integrated circuits Type de document : texte imprimé Auteurs : Michael John Sebastian Smith, Auteur Editeur : Menlo Park, California; Harlow,England; Tokyo : Addison-Wesley Année de publication : 1997 Collection : VLSI Systems Series Importance : 1026 p. Présentation : couv. ill.,ill. Format : 23,2 cm. ISBN/ISSN/EAN : 978-0-321-60275-6 Langues : Anglais (eng) Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : This comprehensive book on application-specific integrated circuits (ASICs) describes the latest methods in VLSI-systems design. ASIC design, using commercial tools and predesigned cell libraries, is the fastest, most cost-effective, and least error-prone method of IC design. As a consequence, ASICs and ASIC-design methods have become increasingly popular in industry for a wide range of applications. The book covers both semicustom and programmable ASIC types. After describing the fundamentals of digital logic design and the physical features of each ASIC type, the book turns to ASIC logic design-design entry, logic synthesis, simulation, and test-and then to physical design-partitioning, floorplanning, placement, and routing. You will find here, in practical, well-explained detail, everything you need to know to understand the design of an ASIC, and everything you must do to begin and to complete your own design. Note de contenu : Contents
1. Introduction to ASICs
2. CMOS Logic.
3. ASIC Library Design.
4. Programmable ASICs.
5. Programmable ASIC Logic Cells.
6. Programmable ASIC I/O Cells.
7. Programmable ASIC Interconnect.
8. Programmable ASIC Design Software.
9. Low-Level Design Entry.
10. VHDL.
11. Verilog HDL.
12. Logic Synthesis.
13. Simulation.
-The Different Types of Simulation.
-Structural Simulation.
-Gate-Level Simulation.
-How Logic Simulation Works.
-VHDL Simulation Cycle.
-SDF in Simulation.
- Switch-Level Simulation.
-Transistor-Level Simulation.
-A PSpice Example.
-SPICE Models.
14. Test.
15. ASIC Construction.
16. Floorplanning and Placement.
17. Routing.
Appendix A. VHDL Resources.
Appendix B. Verilog HDLResources.
-IndexApplication-specific integrated circuits [texte imprimé] / Michael John Sebastian Smith, Auteur . - Menlo Park, California; Harlow,England; Tokyo : Addison-Wesley, 1997 . - 1026 p. : couv. ill.,ill. ; 23,2 cm.. - (VLSI Systems Series) .
ISBN : 978-0-321-60275-6
Langues : Anglais (eng)
Catégories : SEMI CONDUCTEURS Index. décimale : 27-05 Microélectronique Résumé : This comprehensive book on application-specific integrated circuits (ASICs) describes the latest methods in VLSI-systems design. ASIC design, using commercial tools and predesigned cell libraries, is the fastest, most cost-effective, and least error-prone method of IC design. As a consequence, ASICs and ASIC-design methods have become increasingly popular in industry for a wide range of applications. The book covers both semicustom and programmable ASIC types. After describing the fundamentals of digital logic design and the physical features of each ASIC type, the book turns to ASIC logic design-design entry, logic synthesis, simulation, and test-and then to physical design-partitioning, floorplanning, placement, and routing. You will find here, in practical, well-explained detail, everything you need to know to understand the design of an ASIC, and everything you must do to begin and to complete your own design. Note de contenu : Contents
1. Introduction to ASICs
2. CMOS Logic.
3. ASIC Library Design.
4. Programmable ASICs.
5. Programmable ASIC Logic Cells.
6. Programmable ASIC I/O Cells.
7. Programmable ASIC Interconnect.
8. Programmable ASIC Design Software.
9. Low-Level Design Entry.
10. VHDL.
11. Verilog HDL.
12. Logic Synthesis.
13. Simulation.
-The Different Types of Simulation.
-Structural Simulation.
-Gate-Level Simulation.
-How Logic Simulation Works.
-VHDL Simulation Cycle.
-SDF in Simulation.
- Switch-Level Simulation.
-Transistor-Level Simulation.
-A PSpice Example.
-SPICE Models.
14. Test.
15. ASIC Construction.
16. Floorplanning and Placement.
17. Routing.
Appendix A. VHDL Resources.
Appendix B. Verilog HDLResources.
-IndexExemplaires
Code-barres Cote Support Localisation Section Disponibilité N.Inventaire 2432 27-05-10 Livre Bibliothèque de Génie Electrique- USTO Documentaires Exclu du prêt 2432 2433 27-05-10 Livre Bibliothèque de Génie Electrique- USTO Documentaires Exclu du prêt 2433
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