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Computer architecture / Silvia M. Mueller

Public ISBD Titre : Computer architecture : complexity and correctness, with 214 figures and 185 tables Type de document : texte imprimé Auteurs : Silvia M. Mueller, Auteur ; Wolfgang J. Paul, Auteur Editeur : Berlin Heidelberg : Springer-Verlag Année de publication : 2000 Importance : 553 p. Présentation : couv. ill. en coul., ill. Format : 24 cm. ISBN/ISSN/EAN : 978-3-540-67481-8 Langues : Anglais (eng) Catégories : INFORMATIQUE Index. décimale : 08-04 Architecture et théorie des ordinateurs Résumé : Computer Architecture: Complexity and Correctness develops, at the gate level, the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. In contrast to other design approaches applied in practice and unlike other textbooks available, the design presented here are modular, clean and complete up to the construction of entire complex machines. The authors' systematically basing their approach on rigorous mathematical formalisms allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation as well as, generally speaking, for coverage of a broad variety of relevant issues within a reasonable number of pages. The book is written as a text for classes on computer architecture and related topics and will serve as a valuable source of reference for professionals in hardware design. Note de contenu : Contents 1- Introductio 2- Basic 3- A Sequential DLX Desig 4- Basic Pipelines 5- Interrupt Handling 6- Memory System Design 7- IEEE Standard 8- Floating Point Algorithms & Data Paths 9- Pipelined DLX with Floating Point Core A- DLX Instruction Set Architecture B- Specification of the FDLX Design -Bibliography -Index Computer architecture : complexity and correctness, with 214 figures and 185 tables [texte imprimé] / Silvia M. Mueller, Auteur ; Wolfgang J. Paul, Auteur . - Berlin Heidelberg : Springer-Verlag, 2000 . - 553 p. : couv. ill. en coul., ill. ; 24 cm. ISBN : 978-3-540-67481-8 Langues : Anglais (eng) Catégories : INFORMATIQUE Index. décimale : 08-04 Architecture et théorie des ordinateurs Résumé : Computer Architecture: Complexity and Correctness develops, at the gate level, the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. In contrast to other design approaches applied in practice and unlike other textbooks available, the design presented here are modular, clean and complete up to the construction of entire complex machines. The authors' systematically basing their approach on rigorous mathematical formalisms allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation as well as, generally speaking, for coverage of a broad variety of relevant issues within a reasonable number of pages. The book is written as a text for classes on computer architecture and related topics and will serve as a valuable source of reference for professionals in hardware design. Note de contenu : Contents 1- Introductio 2- Basic 3- A Sequential DLX Desig 4- Basic Pipelines 5- Interrupt Handling 6- Memory System Design 7- IEEE Standard 8- Floating Point Algorithms & Data Paths 9- Pipelined DLX with Floating Point Core A- DLX Instruction Set Architecture B- Specification of the FDLX Design -Bibliography -Index

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Code-barres	Cote	Support	Localisation	Section	Disponibilité	N.Inventaire
979	08-04-07	Livre	Bibliothèque de Génie Electrique- USTO	Documentaires	Exclu du prêt	979