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Algorithm for testing physical fallure in VLSI digital circuits / BENATCHBA Karima

Public ISBD Titre : Algorithm for testing physical fallure in VLSI digital circuits Type de document : texte imprimé Auteurs : BENATCHBA Karima, Auteur Année de publication : 1986 Importance : 74 p. Langues : Anglais (eng) Catégories : Physique Mots-clés : VLSI ,digital circuits ,Algorithm Résumé : In this thesis , we will develop and implement an algorithm based on graph theory techniques to generate a test to detect physical faults in VLSI circuits , two types of physical faults are assumed at the transistor circuit level : shorts and opens , by generating a test , we mean assigning states ( 0 or 1) to all the controllable inputs (transistors ) of the digital circuit faults can be checked only one at a time , the algorithm developed is based on first modeling each gate of the network as a directed labeled graph , gauss elimination technique is then used to find paths and cut sets to generate the test assignment ( for the circuit) at the faulted gate ( the operation (+) (.) are redefined using a new path algebra ) finally the assignment made at that particular gate is propagated to the last gate of the network and justified to the first gate of the network , by propagating , we mean creating a sensitized path originating at the fault whose value all along the path is functionally dependent on the process of satisfying assignments by baking up to the ( first gate) Directeur de thèse : MONA.E.ZAGHLOUL Algorithm for testing physical fallure in VLSI digital circuits [texte imprimé] / BENATCHBA Karima, Auteur . - 1986 . - 74 p. Langues : Anglais (eng) Catégories : Physique Mots-clés : VLSI ,digital circuits ,Algorithm Résumé : In this thesis , we will develop and implement an algorithm based on graph theory techniques to generate a test to detect physical faults in VLSI circuits , two types of physical faults are assumed at the transistor circuit level : shorts and opens , by generating a test , we mean assigning states ( 0 or 1) to all the controllable inputs (transistors ) of the digital circuit faults can be checked only one at a time , the algorithm developed is based on first modeling each gate of the network as a directed labeled graph , gauss elimination technique is then used to find paths and cut sets to generate the test assignment ( for the circuit) at the faulted gate ( the operation (+) (.) are redefined using a new path algebra ) finally the assignment made at that particular gate is propagated to the last gate of the network and justified to the first gate of the network , by propagating , we mean creating a sensitized path originating at the fault whose value all along the path is functionally dependent on the process of satisfying assignments by baking up to the ( first gate) Directeur de thèse : MONA.E.ZAGHLOUL

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